1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device providing planarly dispersed charge storing means (for example, charge traps in a nitride film in a MONOS type or MNOS type transistor, charge traps near the interface of a top insulating film and nitride film, small particle size conductors, and so forth) inside of a gate insulating film between a channel forming region and gate electrode of a memory transistor and basically operating to electrically inject charges (electrons or holes) into the charge storing means to store the same or to drain the same and to a process for production and write method for the same.
2. Description of the Related Art
As a nonvolatile semiconductor memory, a floating gate (FG) type nonvolatile semiconductor memory where charge storing means (floating gates) for holding charges are planarly dispersed, and a metal-oxide nitride-oxide semiconductor (MONOS) type nonvolatile semiconductor memory for example where the charge storing means are planarly dispersed are known.
In a MONOS type nonvolatile semiconductor memory, carrier traps in a nitride film (SixNy (0 less than x less than 1, 0 less than y less than 1)) mainly responsible for holding charges or at a boundary (an interface) between a top oxide film and the nitride film spread out spatially dispersedly (that is, in the planar direction and thickness direction), so the charge retention characteristic is dependent on the energy and spatial distribution of the charges captured by the carrier traps in the SixNy film.
When leakage current paths are locally generated in the tunnel insulating film, in the FG type nonvolatile semiconductor memory, a large number of the charges pass through the leakage current paths and the charge retention characteristic tends to decline, while in the MONOS type nonvolatile semiconductor memory, since the charge storing means are spatially dispersed, the local charges around the leakage current paths pass through the leakage current paths and only local leakage occurs so the charge retention characteristic of the storage element as a whole does not easily fall.
Therefore, in the MONOS type nonvolatile semiconductor memory, the problem of the reduction of the charge retention characteristic due to a reduction in the thickness of the tunnel insulating film is not as serious as that in the FG type nonvolatile semiconductor memory. Therefore, the scaling of a tunnel insulating film in a fine memory transistor with an extremely short gate length is better in the MONOS type nonvolatile semiconductor memory than the FG type nonvolatile semiconductor memory.
In a MONOS type nonvolatile semiconductor memory or other nonvolatile semiconductor memory with planarly dispersed charge storing means of the memory transistors, it is essential to realize a one-transistor type of cell structure in order to reduce the cost per bit, increase the degree of integration, and realize a large-sized nonvolatile semiconductor memory.
In a MONOS type nonvolatile semiconductor memory or other nonvolatile semiconductor memory of the related art, however, the mainstream configuration has been for a two-transistor cell with a selected transistor connected to the memory transistor. At the present time, various studies are underway for establishment of single transistor cell technology.
In order to establish such single transistor cell technology, it is necessary to optimize the device structure, primarily the gate insulating film including the charge storing means, and improve the reliability and also to improve the disturbance characteristic. Further, as one measure for improving the disturbance characteristic of a MONOS type nonvolatile semiconductor memory, studies are being conducted on setting the tunnel insulating film thicker (1.6 nm to 2.0 nm).
Further, in order to reduce the cost per bit of a nonvolatile semiconductor memory and increase the integration density, it is necessary to miniaturize the memory cell and also reduce the area of the surrounding circuits. In reducing the area of surrounding circuits, it is important to reduce the write voltage and erase voltage from the viewpoint of ensuring the reliability along with miniaturization of the memory cell and reducing the circuit load of the surrounding circuits. Further, even in a system LSI, where there has been active development going on in recent years, it is becoming important to reduce the operating voltage from the viewpoint of mounting together with logic circuits.
Summarizing the problem, in a MONOS type nonvolatile semiconductor memory or other nonvolatile semiconductor memory with planarly dispersed charge storing means of the related art, setting the tunnel insulating film relatively thick in order to improve the disturbance characteristic limits the reduction of the operating voltage. That is, in a nonvolatile semiconductor memory of the related art, there is a tradeoff between making the tunnel insulating film thicker and reducing the operating voltage while maintaining a fast operating rate. Due to this, it suffers from the problem that it is not possible to simultaneously improve the disturbance characteristic and reduce the operating voltage.
An object of the present invention is to provide a nonvolatile semiconductor memory such as a MONOS type nonvolatile semiconductor memory which operates by storing charges in planarly dispersed carrier traps and which has a better scaling of the tunnel insulating film than the FG type nonvolatile semiconductor memory, where it is possible to reduce the operating voltage while maintaining an excellent disturbance characteristic, and a process for the production of the same.
Another object of the present invention is to provide a write method in a nonvolatile semiconductor memory, including a bias setting method preferable to the cell structure.
According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a substrate; and a plurality of memory transistors formed in the substrate and arranged in a word direction and a bit direction, each memory transistor including: a semiconductor channel forming region formed in the substrate; a gate insulating film formed on the semiconductor channel forming region and comprising a Fowler-Nordheim (FN) type tunneling film which has a FN type tunneling electroconductivity and contains material having a dielectric constant greater than that of silicon oxide; a gate electrode formed on the gate insulating film; and a charge storing means, formed in the gate insulating film, and facing to the surface of the channel forming region.
The FN tunneling film comprises any one of a nitride film, an oxynitride film, and aluminum oxide film, a tantalum pentaoxide film and a BST (BaSrTiO3) film, having an FN tunneling electroconductivity.
The gate insulating film includes a buffer layer formed between the FN tunneling film and the channel forming region and suppressing an interface trap level.
The gate insulating film may comprise a Pool-Frenkel (PF) type film including any one of a nitride film, an oxynitride film, and aluminum oxide film, a tantalum pentaoxide film and a BST (BaSrTiO3) film, having an PN type electroconductivity.
The nonvolatile semiconductor memory device may further comprises a pull-up electrode in the vicinity of the gate electrode or a wiring layer connected to the gate electrode, via a dielectric film; and a pull-up gate bias means for applying a voltage to the pull-up electrode.
A plurality of gate electrodes of the plurality of memory transistors are connected to a plurality of word lines, and a selected transistor is connected between the pull-up gate bias means and the pull-up electrode, the pull-up gate bias means supplying a voltage having a polarity that is the same as a polarity of a boosting voltage for boosting the precharged word line by a capacitance coupling.
The pull-up electrode may be arranged in the vicinity of an upper portion of the gate electrode or a connection layer connected to the gate electrode, via the dielectric film.
Each memory transistor comprises a source region contacted to the channel forming region, and a drain region spaced to the source region and contacted to the channel forming region, a plurality of gate electrodes of the plurality of memory transistors are connected to a plurality of word lines, the source region and drain region of each memory transistor are connected to a common line in a bit direction, electrically insulated to and intersecting to the word line. The nonvolatile semiconductor memory device further comprises a write inhibit voltage supply means for supplying a reverse-biased voltage to the source region and/or the drain region of the memory transistor the gate electrode of which is connected to the word line selected at a writing, through the common line, to make the source region and/or the drain region in a reverse-biased state to the channel forming region, and a non-selected word line biasing means for supplying a voltage to a non-selected word line at the writing, a polarity of the voltage being a polarity making the non-selected word line in a reverse biased state to the channel forming region.
The write inhibit voltage supply means supplies the reverse bias voltage to the source region and/or the drain region to make a bias voltage of the memory transistor connected to the selected word line to thereby prevent an erroneous write and/or an erroneous erase.
The non-selected word line biasing means supplies a voltage having a polarity for reverse-biasing to the non-selected word line to make a bias voltage of the memory transistor connected to the non-selected word line to thereby prevent an erroneous write and/or an erroneous erase.
The non-selected word line biasing means biases the gate electrode to the source region so that a voltage of the gate electrode becomes a low level equal to or lower than an inhibit gate voltage.
When the reverse bias voltage is supplied to the channel forming region while the gate electrode and the channel forming region of the memory transistor are kept at a same potential level, depletion layers extend from the source region and drain region to the channel forming region to merge them.
The gate length of the memory transistor is shorter than a gate length given by, when the reverse bias voltage is supplied while the gate electrode and the channel forming region are kept at a same potential level, a merged depletion layers extended from the source region and the drain region to the channel forming region.
Each memory transistor comprises a source region contacted to the channel forming region, and a drain region spaced to the source region and contacted to the channel forming region, and the nonvolatile semiconductor memory device comprises a source line commonly connecting the plurality of source regions of the plurality of memory transistors in a bit direction.
A bit line commonly connects the plurality of drain regions of the plurality of memory transistors in the bit direction, and a word line commonly connects the plurality of gate electrodes of the plurality of memory transistors in a word direction.
Each memory transistor comprises a source region contacted to the channel forming region, and a drain region spaced to the source region and contacted to the channel forming region, and the nonvolatile semiconductor memory device comprises sub source lines commonly connecting the plurality of source regions of the plurality of memory transistors in a bit direction. A main source line commonly connects the sub source lines in the bit direction, sub bit lines commonly connect the plurality of drain regions of the plurality of memory transistors in the bit direction, a main bit line commonly connecting the sub bit line in the bit direction, and a word line commonly connects the plurality of gate electrodes of the plurality of memory transistors in a word direction. A selected memory transistor is connected between the sub source line and the main source line and between the sub bit line and the main bit line.
The plurality of memory transistors are connected in series between a first selected transistor connected to a bit line and a second selected transistor connected to a common potential line.
Each memory transistor comprises a source region contacted to the channel forming region, and a drain region spaced to the source region and contacted to the channel forming region. The nonvolatile semiconductor memory device comprises a plurality of element separation regions for isolating the respective memory transistors by insulation, a common line commonly connecting the source regions or the drain regions in a bit direction, and a word line connecting the plurality of gate electrodes in a word direction. The plurality of element separation regions are formed as lines along the bit direction and spaced each other, and the common line which intersects and is electrically isolated to the word line, is connected to one of the source region or the drain region, and is wired on the element separation regions by avoiding a wiring passing on another region of the source region or the drain region which is not connected to the common line.
The plurality of element separation regions are formed as parallel strips having a width approximately equal to that of the word line, adjacent strips being spaced as adjacent word lines, a self-aligned contact hole is formed on the source region and the drain region by using a sidewall insulation layer formed on sidewalls of the word line, and the common line wired on the element separation regions is commonly connected to the one region through the self-aligned contact hole and is wired by a winding manner in the bit direction.
The charge storing means does not have conductivity as a whole facing to the channel forming region when charges are not moved to the outside of the memory transistor.
The gate insulating film comprises a tunneling insulating film formed on the channel forming region, and a nitride film or an oxide nitride film, formed on the tunneling insulating film.
The gate insulating film comprises a tunneling insulating film formed on the channel forming region, and conductors including small sized conductive material, formed on the tunneling insulating film as the charge storing means and isolated from each other.
According to a second aspect of the present invention, there is provided a process of producing the nonvolatile semiconductor memory, including steps of: forming a drain region, a source region and a channel forming region arranged between the drain region and the source region and contacted to them; forming a gate insulating film including a charge storing means formed on and facing the surface of the channel forming region; and forming a gate electrode on the gate insulating film, the gate insulating film formation step including a step of forming a Fowler-Nordheim (FN) type tunneling film comprising material having an FN tunneling electroconductivity and having a dielectric constant larger than that of silicon oxide, and the FN tunneling film forming step including a step of heating the FN tunneling film at a high temperature in an atmosphere of a reduction gas and/or oxidation gas.
The process further includes a step of forming a buffer layer formed between the FN tunneling film and the channel forming region and suppressing an interface trap level, before forming the FN tunneling film.
A process further includes a step of forming a Pool-Frenkel (PF) type film including any one of a nitride film, an oxynitride film, and aluminum oxide film, a tantalum pentaoxide film and a BST (BaSrTiO3) film, having an PF electroconductivity, on the FN tunneling film.
A process of further includes a step of forming a PN film on the FN tunneling film via the buffer layer, the PN film comprising any one of a nitride film, an oxynitride film, an aluminum oxide film, a tantalum pentaoxide film and a BST (BaSrTiO3) film, having a PF electroconductivity.
According to a third aspect of the present invention, there is provided a method of writing data into the nonvolatile semiconductor memory device, including a step of applying a voltage to the pull-up electrode to raise a potential of the gate electrode.
A method includes a step of applying a program voltage equal or lower than 10V, to a gate electrode of the selected memory transistor.
A method includes the steps of: supplying a reverse-biased voltage to the source region and/or the drain region of the memory transistor the gate electrode of which is connected to the word line selected at a writing, through the common line, to make the source region and/or the drain region in a reverse-biased state to the channel forming region, and supplying a voltage to a non-selected word line at the writing, a polarity of the voltage being a polarity making the non-selected word line in a reverse-biased state to the channel forming region.
A method includes a step of supplying the reverse-bias voltage to the source region and/or the drain region to make a bias voltage of the memory transistor connected to the selected word line to thereby prevent an erroneous write and/or an erroneous erase.
A method includes a step of supplying a voltage having a polarity for reverse-biasing to the non-selected word line to make a bias voltage of the memory transistor connected to the non-selected word line to thereby prevent an erroneous write and/or an erroneous erase.
A method includes a step of biasing the gate electrode to the source region so that a voltage of the gate electrode becomes a low level equal or lower than an inhibit gate voltage.
When the reverse bias voltage is supplied to the channel forming region, the gate electrode and the channel forming region of the memory transistor are applied by a same voltage.
The reverse bias voltage is applied to the source region via a source line commonly connecting the source regions in the bit direction, and/or, the drain region via a bit line commonly connecting the drain regions in the bit direction, and the voltage having a polarity for reverse-biasing is applied via the word line commonly connecting the gate electrodes in the word direction.
A program voltage is applied to the gate electrode, and a voltage is applied to the pull-up electrode of the selected memory transistor.
A voltage having a polarity for reverse-biasing is applied to the non-selected word line, the reverse-biasing voltage is applied to the source region and/or the drain region of the memory transistor connected to the selected word line, a program voltage is applied to the selected word line, and a voltage is applied to the pull-up electrode.